Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuit (IC) devices are well known in the art and many monolithic structure forms are commercially available. Because such devices can employ circuits that consume very little power, their popularity has grown substantially over the years. However, most applications are digital in nature because in linear operation CMOS circuits are relatively noisy. Accordingly, most linear circuits employ bipolar active devices. For many years Junction Field Effect Transisitor (JFET) devices have been employed in linear IC's to provide circuits having superior characteristics. For example JFET input stages coupled to conventional Bipolar Junction Transistor (BJT) amplifiers provide very high input impedance, low noise operational amplifier (op amp) performance. Such devices have become very popular with equipment designers. In recent years, there has been great interest in building CMOS-based linear circuits because they are lower in cost than bipolar circuits, and because they offer mixed linear and digital functions on the same IC. A key requirement for such CMOS-linear IC's is that they include low noise amplifiers. This disclosure describes an IC structure that solves this low noise amplifier problems.
For CMOS fabrication reference can be made to the Gregorio Spadea U.S. Pat. No. 3,983,620 which was issued Oct. 5, 1976, to the assignee of the present invention. Reference is also made to James B. Compton U.S. Pat. No. 4,176,368 which was issued Nov. 27, 1979, to the assignee of the present invention. Here an improved P-Channel JFET is described for use in conventional bipolar monolithic IC structures. The teaching in the above two patents is incorporated herein by reference.